A System Verilog Rewriting System for RTL Abstraction with Pentium Case Study

Steve Haynal, Timothy Kam, Michael Kishinevsky, Emily Shriver, Xinning Wang. A System Verilog Rewriting System for RTL Abstraction with Pentium Case Study. In 6th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2008), June 5-7, 2008, Anaheim, CA, USA. pages 79-88, IEEE Computer Society, 2008. [doi]

Abstract

Abstract is missing.