Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/ CMOS process - researchr publication authors

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Peter Hazucha, Tanay Karnik, Steven Walstra, Bradley A. Bloechel, James W. Tschanz, Jose Maiz, Krishnamurthy Soumyanath, Gregory E. Dermer, Siva G. Narendra, Vivek De, Shekhar Borkar. Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/ CMOS process. J. Solid-State Circuits, 39(9):1536-1543, 2004. [doi]

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