Accelerating Low Bit-Width Deep Convolution Neural Network in MRAM

Zhezhi He, Shaahin Angizi, Deliang Fan. Accelerating Low Bit-Width Deep Convolution Neural Network in MRAM. In 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018, Hong Kong, China, July 8-11, 2018. pages 533-538, IEEE Computer Society, 2018. [doi]

@inproceedings{HeAF18,
  title = {Accelerating Low Bit-Width Deep Convolution Neural Network in MRAM},
  author = {Zhezhi He and Shaahin Angizi and Deliang Fan},
  year = {2018},
  doi = {10.1109/ISVLSI.2018.00103},
  url = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2018.00103},
  researchr = {https://researchr.org/publication/HeAF18},
  cites = {0},
  citedby = {0},
  pages = {533-538},
  booktitle = {2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018, Hong Kong, China, July 8-11, 2018},
  publisher = {IEEE Computer Society},
  isbn = {978-1-5386-7099-6},
}