Encoder architecture with throughput over 10 Gbit/sec for quasi-cyclic LDPC codes

Zhiyong He, Sébastien Roy, Paul Fortier. Encoder architecture with throughput over 10 Gbit/sec for quasi-cyclic LDPC codes. In International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece. IEEE, 2006. [doi]

Authors

Zhiyong He

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Sébastien Roy

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Paul Fortier

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