Antti Heiskanen, Antti Mäntyniemi, Timo Rahkonen. A 30 MHz DDS clock generator with sub-ns time domain interpolator and -50 dBc spurious level. In International Symposium on Circuits and Systems (ISCAS 2001), 6-9 May 2001, Sydney, Australia. pages 626-629, IEEE, 2001. [doi]
@inproceedings{HeiskanenMR01,
title = {A 30 MHz DDS clock generator with sub-ns time domain interpolator and -50 dBc spurious level},
author = {Antti Heiskanen and Antti Mäntyniemi and Timo Rahkonen},
year = {2001},
doi = {10.1109/ISCAS.2001.922315},
url = {http://doi.ieeecomputersociety.org/10.1109/ISCAS.2001.922315},
researchr = {https://researchr.org/publication/HeiskanenMR01},
cites = {0},
citedby = {0},
pages = {626-629},
booktitle = {International Symposium on Circuits and Systems (ISCAS 2001), 6-9 May 2001, Sydney, Australia},
publisher = {IEEE},
isbn = {0-7803-6685-9},
}