A 30 MHz DDS clock generator with sub-ns time domain interpolator and -50 dBc spurious level - researchr publication

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Antti Heiskanen, Antti Mäntyniemi, Timo Rahkonen. A 30 MHz DDS clock generator with sub-ns time domain interpolator and -50 dBc spurious level. In International Symposium on Circuits and Systems (ISCAS 2001), 6-9 May 2001, Sydney, Australia. pages 626-629, IEEE, 2001. [doi]

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