Saied Hemati. Mitigating hardware cyber-security risks in error correcting decoders. In 9th International Symposium on Turbo Codes and Iterative Information Processing, ISTC 2016, Brest, France, September 5-9, 2016. pages 181-185, IEEE, 2016. [doi]
@inproceedings{Hemati16,
title = {Mitigating hardware cyber-security risks in error correcting decoders},
author = {Saied Hemati},
year = {2016},
doi = {10.1109/ISTC.2016.7593101},
url = {http://dx.doi.org/10.1109/ISTC.2016.7593101},
researchr = {https://researchr.org/publication/Hemati16},
cites = {0},
citedby = {0},
pages = {181-185},
booktitle = {9th International Symposium on Turbo Codes and Iterative Information Processing, ISTC 2016, Brest, France, September 5-9, 2016},
publisher = {IEEE},
isbn = {978-1-5090-3401-7},
}