Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja. Fault simulation and test generation for clock delay faults. In Proceedings of the 16th Asia South Pacific Design Automation Conference, ASP-DAC 2011, Yokohama, Japan, January 25-27, 2011. pages 799-805, IEEE, 2011. [doi]
Abstract is missing.