Leakage power reduction for coarse-grained dynamically reconfigurable processor arrays using Dual Vt cells

Keiichiro Hirai, Masaru Kato, Yoshiki Saito, Hideharu Amano. Leakage power reduction for coarse-grained dynamically reconfigurable processor arrays using Dual Vt cells. In Neil W. Bergmann, Oliver Diessel, Lesley Shannon, editors, Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT 2009, Sydney, Australia, December 9-11, 2009. pages 104-111, IEEE Computer Society, 2009. [doi]

Authors

Keiichiro Hirai

This author has not been identified. Look up 'Keiichiro Hirai' in Google

Masaru Kato

This author has not been identified. Look up 'Masaru Kato' in Google

Yoshiki Saito

This author has not been identified. Look up 'Yoshiki Saito' in Google

Hideharu Amano

This author has not been identified. Look up 'Hideharu Amano' in Google