Abstract is missing.
- Packets everywhere: The great opportunity for field programmable technologyGordon J. Brebner. 1-10 [doi]
- From dynamic reconfiguration to self-reconfiguration: Invasive algorithms and architecturesJürgen Teich. 11-12 [doi]
- ASKAP beamformerJohn D. Bunton. 13 [doi]
- Design of a Vehicle-to-Vehicle communication system on reconfigurable hardwareOliver Sander, Benjamin Glas, Christoph Roth, Jürgen Becker, Klaus D. Müller-Glaser. 14-21 [doi]
- Implementation of a foveal vision mappingDonald G. Bailey, Christos-Savvas Bouganis. 22-29 [doi]
- An architecture of optimised SIFT feature detection for an FPGA implementation of an image matcherLifan Yao, Hao Feng, Yiqun Zhu, Zhiguo Jiang, Danpei Zhao, Wenquan Feng. 30-37 [doi]
- Exploiting memory customization in FPGA for 3D stencil computationsMuhammad Shafiq, Miquel Pericàs, Raúl de la Cruz, Mauricio Araya-Polo, Nacho Navarro, Eduard Ayguadé. 38-45 [doi]
- Towards a balanced ternary FPGAPaul Beckett. 46-53 [doi]
- Concurrently optimizing FPGA architecture parameters and transistor sizing: Implications for FPGA designAlastair M. Smith, George A. Constantinides, Steven J. E. Wilton, Peter Y. K. Cheung. 54-61 [doi]
- Simulation of a QCA-based CLB and a multi-CLB applicationChia-Ching Tung, Ruchi B. Rungta, Eric Peskin. 62-69 [doi]
- A flexible DSP block to enhance FPGA arithmetic performanceHadi Parandeh-Afshar, Alessandro Cevrero, Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leblebici, Paolo Ienne. 70-77 [doi]
- VMATCH: Using logical variation to counteract physical variation in bottom-up, nanoscale systemsBenjamin Gojman, André DeHon. 78-87 [doi]
- PGR: Period and glitch reduction via clock skew scheduling, delay padding and GlitchLessXiao Dong, Guy G. F. Lemieux. 88-95 [doi]
- A detailed delay path model for FPGAsEddie Hung, Steven J. E. Wilton, Haile Yu, Thomas C. P. Chau, Philip Heng Wai Leong. 96-103 [doi]
- Leakage power reduction for coarse-grained dynamically reconfigurable processor arrays using Dual Vt cellsKeiichiro Hirai, Masaru Kato, Yoshiki Saito, Hideharu Amano. 104-111 [doi]
- ASIF: Application Specific Inflexible FPGAHusain Parvez, Zied Marrakchi, Habib Mehrez. 112-119 [doi]
- The challenges of using an embedded MPI for hardware-based processing nodesDaniel Le Ly, Manuel Saldaña, Paul Chow. 120-127 [doi]
- Transforming write collisions in block RAMs into security applicationsTim Güneysu, Christof Paar. 128-134 [doi]
- FPGA implementation of an invasive computing architectureAbdulazim Amouri, Farhadur Arifin, Frank Hannig, Jürgen Teich. 135-142 [doi]
- FFPU: Fractured floating point unit for FPGA soft processorsNeil Hockert, Katherine Compton. 143-150 [doi]
- Rapid synthesis and simulation of computational circuits in an MPPADavid Grant, Graeme Smecher, Guy Lemieux, Rosemary Francis. 151-158 [doi]