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An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads

Hiroaki Hirata, Kozo Kimura, Satoshi Nagamine, Yoshiyuki Mochizuki, Akio Nishimura, Yoshimori Nakase, Teiji Nishizawa. An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads. In ISCA. pages 136-145, 1992.

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