Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic - researchr publication authors

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Weng-Geng Ho, Kwen-Siong Chong, Tong Lin, Bah-Hwee Gwee, Joseph S. Chang. Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic. In 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea (South), May 20-23, 2012. pages 492-495, IEEE, 2012. [doi]

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