Intra-masking dual-rail memory on LUT implementation for tamper-resistant AES on FPGA - researchr publication authors

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Anh Tuan Hoang, Takeshi Fujino. Intra-masking dual-rail memory on LUT implementation for tamper-resistant AES on FPGA. In Katherine Compton, Brad L. Hutchings, editors, Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, FPGA 2012, Monterey, California, USA, February 22-24, 2012. pages 1-10, ACM, 2012. [doi]

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