An FPGA-Based Accelerator to Speed-Up Matrix Multiplication of Floating Point Operations

B. Holanda, R. Pimentel, J. Barbosa, R. Camarotti, A. Silva-Filho, L. João, V. Souza, J. Ferraz, M. Lima. An FPGA-Based Accelerator to Speed-Up Matrix Multiplication of Floating Point Operations. In 25th IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2011, Anchorage, Alaska, USA, 16-20 May 2011 - Workshop Proceedings. pages 306-309, IEEE, 2011. [doi]

@inproceedings{HolandaPBCSJSFL11,
  title = {An FPGA-Based Accelerator to Speed-Up Matrix Multiplication of Floating Point Operations},
  author = {B. Holanda and R. Pimentel and J. Barbosa and R. Camarotti and A. Silva-Filho and L. João and V. Souza and J. Ferraz and M. Lima},
  year = {2011},
  doi = {10.1109/IPDPS.2011.165},
  url = {http://doi.ieeecomputersociety.org/10.1109/IPDPS.2011.165},
  researchr = {https://researchr.org/publication/HolandaPBCSJSFL11},
  cites = {0},
  citedby = {0},
  pages = {306-309},
  booktitle = {25th IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2011, Anchorage, Alaska, USA, 16-20 May 2011 - Workshop Proceedings},
  publisher = {IEEE},
  isbn = {978-1-61284-425-1},
}