An FPGA-Based Accelerator to Speed-Up Matrix Multiplication of Floating Point Operations

B. Holanda, R. Pimentel, J. Barbosa, R. Camarotti, A. Silva-Filho, L. João, V. Souza, J. Ferraz, M. Lima. An FPGA-Based Accelerator to Speed-Up Matrix Multiplication of Floating Point Operations. In 25th IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2011, Anchorage, Alaska, USA, 16-20 May 2011 - Workshop Proceedings. pages 306-309, IEEE, 2011. [doi]

Abstract

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