Glenn Holt, Akhilesh Tyagi. Minimizing interconnect energy through integrated low-power placement and combinational logic synthesis. In ISPD. pages 48-53, 1997. [doi]
@inproceedings{HoltT97,
title = {Minimizing interconnect energy through integrated low-power placement and combinational logic synthesis},
author = {Glenn Holt and Akhilesh Tyagi},
year = {1997},
doi = {10.1145/267665.267679},
url = {http://doi.acm.org/10.1145/267665.267679},
tags = {logic},
researchr = {https://researchr.org/publication/HoltT97},
cites = {0},
citedby = {0},
pages = {48-53},
booktitle = {ISPD},
}