Incorporating Power Reduction Mechanism in Arithmetic Core Design - researchr publication authors

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Sangjin Hong, Shu-Shin Chin. Incorporating Power Reduction Mechanism in Arithmetic Core Design. In 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), Emerging Trends in VLSI Systems Design, 19-20 February 2004, Lafayette, LA, USA. pages 249-250, IEEE Computer Society, 2004. [doi]

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