Sangjin Hong, Shu-Shin Chin. Incorporating Power Reduction Mechanism in Arithmetic Core Design. In 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), Emerging Trends in VLSI Systems Design, 19-20 February 2004, Lafayette, LA, USA. pages 249-250, IEEE Computer Society, 2004. [doi]
@inproceedings{HongC04:1,
title = {Incorporating Power Reduction Mechanism in Arithmetic Core Design},
author = {Sangjin Hong and Shu-Shin Chin},
year = {2004},
url = {http://csdl.computer.org/comp/proceedings/isvlsi/2004/2097/00/20970249abs.htm},
tags = {design},
researchr = {https://researchr.org/publication/HongC04%3A1},
cites = {0},
citedby = {0},
pages = {249-250},
booktitle = {2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), Emerging Trends in VLSI Systems Design, 19-20 February 2004, Lafayette, LA, USA},
publisher = {IEEE Computer Society},
isbn = {0-7695-2097-9},
}