Tadayoshi Horita, Itsuo Takanami. Fault Tolerant Processor Arrays Based on 1 1/2-Track Switch with Generalized Spare Distributions. In 1999 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN 99), 23-25 June 1999, Fremantle, Australia. pages 135-137, IEEE Computer Society, 1999. [doi]
@inproceedings{HoritaT99,
title = {Fault Tolerant Processor Arrays Based on 1 1/2-Track Switch with Generalized Spare Distributions},
author = {Tadayoshi Horita and Itsuo Takanami},
year = {1999},
url = {http://csdl.computer.org/comp/proceedings/ispan/1999/0231/00/02310135abs.htm},
tags = {rule-based},
researchr = {https://researchr.org/publication/HoritaT99},
cites = {0},
citedby = {0},
pages = {135-137},
booktitle = {1999 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN 99), 23-25 June 1999, Fremantle, Australia},
publisher = {IEEE Computer Society},
isbn = {0-7695-0231-8},
}