Kohei Hosokawa, Katsunori Tanaka, Yuichi Nakamura. Efficient Memory Utilization for High-Speed FPGA-Based Hardware Emulators with SDRAMs. IEICE Transactions, 90-A(12):2810-2817, 2007. [doi]
@article{HosokawaTN07,
title = {Efficient Memory Utilization for High-Speed FPGA-Based Hardware Emulators with SDRAMs},
author = {Kohei Hosokawa and Katsunori Tanaka and Yuichi Nakamura},
year = {2007},
doi = {10.1093/ietfec/e90-a.12.2810},
url = {http://dx.doi.org/10.1093/ietfec/e90-a.12.2810},
tags = {rule-based},
researchr = {https://researchr.org/publication/HosokawaTN07},
cites = {0},
citedby = {0},
journal = {IEICE Transactions},
volume = {90-A},
number = {12},
pages = {2810-2817},
}