A 35 mW 10 Gb/s ADC-DSP less direct digital sequence detector and equalizer in 65nm CMOS

A. K. M. Delwar Hossain, Aurangozeb, Maruf Mohammad, Masum Hossain. A 35 mW 10 Gb/s ADC-DSP less direct digital sequence detector and equalizer in 65nm CMOS. In 2016 IEEE Symposium on VLSI Circuits, VLSIC 2016, Honolulu, HI, USA, June 15-17, 2016. pages 1-2, IEEE, 2016. [doi]

@inproceedings{HossainAMH16,
  title = {A 35 mW 10 Gb/s ADC-DSP less direct digital sequence detector and equalizer in 65nm CMOS},
  author = {A. K. M. Delwar Hossain and Aurangozeb and Maruf Mohammad and Masum Hossain},
  year = {2016},
  doi = {10.1109/VLSIC.2016.7573520},
  url = {http://dx.doi.org/10.1109/VLSIC.2016.7573520},
  researchr = {https://researchr.org/publication/HossainAMH16},
  cites = {0},
  citedby = {0},
  pages = {1-2},
  booktitle = {2016 IEEE Symposium on VLSI Circuits, VLSIC 2016, Honolulu, HI, USA, June 15-17, 2016},
  publisher = {IEEE},
  isbn = {978-1-5090-0635-9},
}