Nahid M. Hossain, Arif Iqbal, Hemanshu Shishupal, Masud H. Chowdhury. Tunneling transistor based 6T SRAM bitcell circuit design in sub-10nm domain. In IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017, Boston, MA, USA, August 6-9, 2017. pages 1485-1488, IEEE, 2017. [doi]
@inproceedings{HossainISC17,
title = {Tunneling transistor based 6T SRAM bitcell circuit design in sub-10nm domain},
author = {Nahid M. Hossain and Arif Iqbal and Hemanshu Shishupal and Masud H. Chowdhury},
year = {2017},
doi = {10.1109/MWSCAS.2017.8053215},
url = {https://doi.org/10.1109/MWSCAS.2017.8053215},
researchr = {https://researchr.org/publication/HossainISC17},
cites = {0},
citedby = {0},
pages = {1485-1488},
booktitle = {IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017, Boston, MA, USA, August 6-9, 2017},
publisher = {IEEE},
isbn = {978-1-5090-6389-5},
}