Hsuan Hsiao, Jason Helge Anderson. Sensei: An area-reduction advisor for FPGA high-level synthesis. In 2018 Design, Automation & Test in Europe Conference & Exhibition, DATE 2018, Dresden, Germany, March 19-23, 2018. pages 25-30, IEEE, 2018. [doi]
@inproceedings{HsiaoA18,
title = {Sensei: An area-reduction advisor for FPGA high-level synthesis},
author = {Hsuan Hsiao and Jason Helge Anderson},
year = {2018},
doi = {10.23919/DATE.2018.8341974},
url = {https://doi.org/10.23919/DATE.2018.8341974},
researchr = {https://researchr.org/publication/HsiaoA18},
cites = {0},
citedby = {0},
pages = {25-30},
booktitle = {2018 Design, Automation & Test in Europe Conference & Exhibition, DATE 2018, Dresden, Germany, March 19-23, 2018},
publisher = {IEEE},
isbn = {978-3-9819263-0-9},
}