A clock recovery circuit for blind equalization multi-Gbps serial data links

Jiawen Hu. A clock recovery circuit for blind equalization multi-Gbps serial data links. In International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece. IEEE, 2006. [doi]

@inproceedings{Hu06-0,
  title = {A clock recovery circuit for blind equalization multi-Gbps serial data links},
  author = {Jiawen Hu},
  year = {2006},
  doi = {10.1109/ISCAS.2006.1693795},
  url = {http://dx.doi.org/10.1109/ISCAS.2006.1693795},
  tags = {data-flow},
  researchr = {https://researchr.org/publication/Hu06-0},
  cites = {0},
  citedby = {0},
  booktitle = {International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece},
  publisher = {IEEE},
}