Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Bo Hu, Jingxiang Tian, Mustafa M. Shihab, Gaurav Rajavendra Reddy, William Swartz, Yiorgos Makris, Benjamin Carrión Schäfer, Carl Sechen. Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA. In Houman Homayoun, Baris Taskin, Tinoosh Mohsenin, Weisheng Zhao, editors, Proceedings of the 2019 on Great Lakes Symposium on VLSI, GLSVLSI 2019, Tysons Corner, VA, USA, May 9-11, 2019. pages 171-176, ACM, 2019. [doi]

This author has not been identified. Look up 'Bo Hu' in GoogleThis author has not been identified. Look up 'Jingxiang Tian' in GoogleThis author has not been identified. Look up 'Mustafa M. Shihab' in GoogleThis author has not been identified. Look up 'Gaurav Rajavendra Reddy' in GoogleThis author has not been identified. Look up 'William Swartz' in GoogleThis author has not been identified. Look up 'Yiorgos Makris' in GoogleThis author has not been identified. Look up 'Benjamin Carrión Schäfer' in GoogleThis author has not been identified. Look up 'Carl Sechen' in Google

runs on WebDSL