Weiwu Hu, Peisu Xia. Event Ordering Condition for Correct Executions in Shared-Memory Systems. In 1996 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN 96), June 12-14, 1996, Beijing, China. pages 84-89, IEEE Computer Society, 1996. [doi]
@inproceedings{HuX96:0,
title = {Event Ordering Condition for Correct Executions in Shared-Memory Systems},
author = {Weiwu Hu and Peisu Xia},
year = {1996},
url = {http://csdl.computer.org/comp/proceedings/ispan/1996/7460/00/74600084abs.htm},
researchr = {https://researchr.org/publication/HuX96%3A0},
cites = {0},
citedby = {0},
pages = {84-89},
booktitle = {1996 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN 96), June 12-14, 1996, Beijing, China},
publisher = {IEEE Computer Society},
}