The acceleration of pipeline workloads under the FPGA area and bandwidth constraints

Wei-Ning Huang, Sheng-Wei Cheng, Che-Wei Chang, Yu-Chen Wu, Tei-Wei Kuo, Yung-Chin Hsu, Wen-Yih Isaac Tseng, Shih-Hao Hung. The acceleration of pipeline workloads under the FPGA area and bandwidth constraints. In 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, Chongqing, China, August 20-22, 2014. pages 1-9, IEEE, 2014. [doi]

@inproceedings{HuangCCWKHTH14,
  title = {The acceleration of pipeline workloads under the FPGA area and bandwidth constraints},
  author = {Wei-Ning Huang and Sheng-Wei Cheng and Che-Wei Chang and Yu-Chen Wu and Tei-Wei Kuo and Yung-Chin Hsu and Wen-Yih Isaac Tseng and Shih-Hao Hung},
  year = {2014},
  doi = {10.1109/RTCSA.2014.6910539},
  url = {http://dx.doi.org/10.1109/RTCSA.2014.6910539},
  researchr = {https://researchr.org/publication/HuangCCWKHTH14},
  cites = {0},
  citedby = {0},
  pages = {1-9},
  booktitle = {2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, Chongqing, China, August 20-22, 2014},
  publisher = {IEEE},
}