Shi-Yu Huang, Tzu-Heng Huang, Kun-Han Tsai, Wu-Tung Cheng. A wide-range clock signal generation scheme for speed grading of a logic core. In International Conference on High Performance Computing & Simulation, HPCS 2016, Innsbruck, Austria, July 18-22, 2016. pages 125-129, IEEE, 2016. [doi]
Abstract is missing.