Zhangcai Huang, Atsushi Kurokawa, Jun Pan, Yasuaki Inoue. Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew. IEICE Transactions, 88-A(12):3367-3374, 2005. [doi]
@article{HuangKPI05,
title = {Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew},
author = {Zhangcai Huang and Atsushi Kurokawa and Jun Pan and Yasuaki Inoue},
year = {2005},
doi = {10.1093/ietfec/e88-a.12.3367},
url = {http://dx.doi.org/10.1093/ietfec/e88-a.12.3367},
tags = {modeling},
researchr = {https://researchr.org/publication/HuangKPI05},
cites = {0},
citedby = {0},
journal = {IEICE Transactions},
volume = {88-A},
number = {12},
pages = {3367-3374},
}