Mitigating Write Disturbance in Phase Change Memory Architectures - researchr publication related

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Chao-Hsuan Huang, Ishan G. Thakkar. Mitigating Write Disturbance in Phase Change Memory Architectures. In 2019 International Conference on Compliers, Architectures and Synthesis for Embedded Systems, CASES 2019, Work in Progress Papers, New York, NY, USA, October 13-18, 2019. pages 1-2, IEEE, 2019. [doi]

The following publications are possibly variants of this publication:

DyPhase: A Dynamic Phase Change Memory Architecture with Symmetric Write LatencyIshan G. Thakkar, Sudeep Pasricha. vlsid 2017: 41-46 [doi]

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