Diagnosing arbitrary defects in logic designs using single location at a time (SLAT)

Leendert M. Huisman. Diagnosing arbitrary defects in logic designs using single location at a time (SLAT). IEEE Trans. on CAD of Integrated Circuits and Systems, 23(1):91-101, 2004. [doi]

@article{Huisman04,
  title = {Diagnosing arbitrary defects in logic designs using single location at a time (SLAT)},
  author = {Leendert M. Huisman},
  year = {2004},
  doi = {10.1109/TCAD.2003.816206},
  url = {http://doi.ieeecomputersociety.org/10.1109/TCAD.2003.816206},
  tags = {logic},
  researchr = {https://researchr.org/publication/Huisman04},
  cites = {0},
  citedby = {0},
  journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
  volume = {23},
  number = {1},
  pages = {91-101},
}