Abstract is missing.
- GPU evolution: will graphics morph into compute?Norm Rubin. 1 [doi]
- Outer-loop vectorization: revisited for short SIMD architecturesDorit Nuzman, Ayal Zaks. 2-11 [doi]
- Redundancy elimination revisitedKeith D. Cooper, Jason Eckhardt, Ken Kennedy. 12-21 [doi]
- Exploiting loop-dependent stream reuse for stream processorsXuejun Yang, Ying Zhang, Jingling Xue, Ian Rogers, Gen Li, Guibin Wang. 22-31 [doi]
- Feature selection and policy optimization for distributed instruction placement using reinforcement learningKatherine E. Coons, Behnam Robatmili, Matthew E. Taylor, Bertrand A. Maher, Doug Burger, Kathryn S. McKinley. 32-42 [doi]
- Core cannibalization architecture: improving lifetime chip performance for multicore processors in the presence of hard faultsBogdan F. Romanescu, Daniel J. Sorin. 43-51 [doi]
- Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessorHenry Wong, Anne Bracy, Ethan Schuchman, Tor M. Aamodt, Jamison D. Collins, Perry H. Wang, Gautham N. Chinya, Ankur Khandelwal Groen, Hong Jiang, Hong Wang 0003. 52-61 [doi]
- Skewed redundancyGordon B. Bell, Mikko H. Lipasti. 62-71 [doi]
- The PARSEC benchmark suite: characterization and architectural implicationsChristian Bienia, Sanjeev Kumar, Jaswinder Pal Singh, Kai Li. 72-81 [doi]
- Visualizing potential parallelism in sequential programsGraham D. Price, John Giacomoni, Manish Vachharajani. 82-90 [doi]
- Characterizing and modeling the behavior of context switch missesFang Liu, Fei Guo, Yan Solihin, Seongbeom Kim, Abdulaziz Eker. 91-101 [doi]
- MCAMP: communication optimization on massively parallel machines with hierarchical scratch-pad memoryHiroshige Hayashizaki, Yutaka Sugawara, Mary Inaba, Kei Hiraki. 102-111 [doi]
- Profiler and compiler assisted adaptive I/O prefetching for shared storage cachesSeung Woo Son, Sai Prashanth Muralidhara, Ozcan Ozturk, Mahmut T. Kandemir, Ibrahim Kolcu, Mustafa Karaköy. 112-121 [doi]
- Runtime optimization of vector operations on large scale SMP clustersCostin Iancu, Steven Hofmeyr. 122-132 [doi]
- (How) can programmers conquer the multicore menace?Saman P. Amarasinghe. 133 [doi]
- Distributed cooperative cachingEnric Herrero, José González, Ramon Canal. 134-143 [doi]
- Scalable and reliable communication for hardware transactional memorySeth H. Pugsley, Manu Awasthi, Niti Madan, Naveen Muralimanohar, Rajeev Balasubramonian. 144-154 [doi]
- Improving support for locality and fine-grain sharing in chip multiprocessorsHemayet Hossain, Sandhya Dwarkadas, Michael C. Huang. 155-165 [doi]
- Edge-centric modulo scheduling for coarse-grained reconfigurable architecturesHyunchul Park, Kevin Fan, Scott A. Mahlke, Taewook Oh, Heeseok Kim, Hong-seok Kim. 166-176 [doi]
- Multi-optimization power management for chip multiprocessorsKe Meng, Russ Joseph, Robert P. Dick, Li Shang. 177-186 [doi]
- Multitasking workload scheduling on flexible-core chip multiprocessorsDivya Gulati, Changkyu Kim, Simha Sethumadhavan, Stephen W. Keckler, Doug Burger. 187-196 [doi]
- Leveraging on-chip networks for data cache migration in chip multiprocessorsNoel Eisley, Li-Shiuan Peh, Li Shang. 197-207 [doi]
- Adaptive insertion policies for managing shared cachesAamer Jaleel, William Hasenplaugh, Moinuddin K. Qureshi, Julien Sebot, Simon C. Steely Jr., Joel S. Emer. 208-219 [doi]
- Analysis and approximation of optimal co-scheduling on chip multiprocessorsYunlian Jiang, Xipeng Shen, Jie Chen, Rahul Tripathi. 220-229 [doi]
- An adaptive resource partitioning algorithm for SMT processorsHuaping Wang, Israel Koren, C. Mani Krishna. 230-239 [doi]
- Meeting points: using thread criticality to adapt multicore hardware to parallel regionsQiong Cai, José González, Ryan Rakvic, Grigorios Magklis, Pedro Chaparro, Antonio González. 240-249 [doi]
- Prediction models for multi-dimensional power-performance optimization on many coresMatthew Curtis-Maury, Ankur Shah, Filip Blagojevic, Dimitrios S. Nikolopoulos, Bronis R. de Supinski, Martin Schulz. 250-259 [doi]
- Mars: a MapReduce framework on graphics processorsBingsheng He, Wenbin Fang, Qiong Luo, Naga K. Govindaraju, Tuyong Wang. 260-269 [doi]
- Multi-mode energy management for multi-tier server clustersTibor Horvath, Kevin Skadron. 270-279 [doi]
- A tuning framework for software-managed memory hierarchiesManman Ren, Ji Young Park, Mike Houston, Alex Aiken, William J. Dally. 280-291 [doi]
- Hybrid access-specific software cache techniques for the cell BE architectureMarc González, Nikola Vujic, Xavier Martorell, Eduard Ayguadé, Alexandre E. Eichenberger, Tong Chen, Zehra Sura, Tao Zhang, Kevin O Brien, Kathryn M. O Brien. 292-302 [doi]
- COMIC: a coherent shared memory interface for cell beJaejin Lee, Sangmin Seo, Chihun Kim, Junghyun Kim, Posung Chun, Zehra Sura, Jungwon Kim, Sangyong Han. 303-314 [doi]