Table of Contents

• RCU-HTM: Combining RCU with HTM to Implement Highly Efficient Concurrent Binary Search TreesDimitrios Siakavaras, Konstantinos Nikas, Georgios I. Goumas, Nectarios Koziris. 1-13 [doi]
• Redesigning Go's Built-In Map to Support Concurrent OperationsLouis Jenkins, Tingzhe Zhou, Michael F. Spear. 14-26 [doi]
• MultiGraph: Efficient Graph Processing on GPUsChangwan Hong, Aravind Sukumaran-Rajam, Jinsung Kim, P. Sadayappan. 27-40 [doi]
• An Ultra Low-Power Hardware Accelerator for Acoustic Scoring in Speech RecognitionHamid Tabani, Jose-Maria Arnau, Jordi Tubella, Antonio González 0001. 41-52 [doi]
• DrMP: Mixed Precision-Aware DRAM for High Performance Approximate and Precise ComputingXianWei Zhang, Youtao Zhang, Bruce R. Childers, Jun Yang. 53-63 [doi]
• SAM: Optimizing Multithreaded Cores for Speculative ParallelismMaleen Abeydeera, Suvinay Subramanian, Mark C. Jeffrey, Joel S. Emer, Daniel Sánchez 0003. 64-78 [doi]
• Performance Improvement via Always-Abort HTMJoseph Izraelevitz, Lingxiang Xiang, Michael L. Scott. 79-90 [doi]
• DRUT: An Efficient Turbo Boost Solution via Load Balancing in Decoupled Look-Ahead ArchitectureRaj Parihar, Michael C. Huang. 91-104 [doi]
• Proxy Benchmarks for Emerging Big-Data WorkloadsReena Panda, Lizy Kurian John. 105-116 [doi]
• Lightweight Provenance Service for High-Performance ComputingDong Dai, Yong Chen, Philip H. Carns, John Jenkins, Robert B. Ross. 117-129 [doi]
• POSTER: Putting the G back into GPU/CPU Systems ResearchAndreas Sembrant, Trevor E. Carlson, Erik Hagersten, David Black-Schaffer. 130-131 [doi]
• POSTER: Application-Driven Near-Data Processing for Similarity SearchVincent T. Lee, Amrita Mazumdar, Carlo C. del Mundo, Armin Alaghi, Luis Ceze, Mark Oskin. 132-133 [doi]
• POSTER: Improving Datacenter Efficiency Through Partitioning-Aware SchedulingHarshad Kasture, Xu Ji, Nosayba El-Sayed, Nathan Beckmann, Xiaosong Ma, Daniel Sánchez 0003. 134-135 [doi]
• POSTER: The Liberation Day of Nondeterministic ProgramsEnrico Armenio Deiana, Vincent St-Amour, Peter Dinda, Nikos Hardavellas, Simone Campanoni. 136-137 [doi]
• POSTER: Location-Aware Computation Mapping for Manycore ProcessorsOrhan Kislal, Jagadish Kotra, Xulong Tang, Mahmut Taylan Kandemir, Myoungsoo Jung. 138-139 [doi]
• POSTER: BACM: Barrier-Aware Cache Management for Irregular Memory-Intensive GPGPU WorkloadsYuxi Liu, Xia Zhao, Zhibin Yu, Zhenlin Wang, Xiaolin Wang, Yingwei Luo, Lieven Eeckhout. 140-141 [doi]
• POSTER: DaQueue: A Data-Aware Work-Queue Design for GPGPUsYa-shuai Lü, Libo Huang, Li Shen. 142-143 [doi]
• POSTER: Accelerate GPU Concurrent Kernel Execution by Mitigating Memory Pipeline StallsHongwen Dai, Zhen Lin, Chao Li, Chen Zhao, Fei Wang, Nanning Zheng, Huiyang Zhou. 144-145 [doi]
• POSTER: Design Space Exploration for Performance Optimization of Deep Neural Networks on Shared Memory AcceleratorsSwagath Venkataramani, Jungwook Choi, Vijayalakshmi Srinivasan, Kailash Gopalakrishnan, Leland Chang. 146-147 [doi]
• POSTER: Bridge the Gap Between Neural Networks and Neuromorphic HardwareYu Ji, Youhui Zhang, Wenguang Chen, Yuan Xie. 148-149 [doi]
• POSTER: Improving NUMA System Efficiency with a Utilization-Based Co-schedulingYounghyun Cho, Camilo A. Celis Guzman, Bernhard Egger. 150-151 [doi]
• POSTER: Bridging the Gap Between Deep Learning and Sparse Matrix Format SelectionYue Zhao, Jiajia Li, Chunhua Liao, Xipeng Shen. 152-153 [doi]
• POSTER: Cutting the Fat: Speeding Up RBM for Fast Deep Learning Through Generalized Redundancy EliminationLin Ning, Randall Pittman, Xipeng Shen. 154-155 [doi]
• POSTER: Exploiting Approximations for Energy/Quality Tradeoffs in Service-Based ApplicationsLiu Liu, Sibren Isaacman, Abhishek Bhattacharjee, Ulrich Kremer. 156-157 [doi]
• POSTER: Statement Reordering to Alleviate Register Pressure for Stencils on GPUsPrashant Singh Rawat, Aravind Sukumaran-Rajam, Atanas Rountev, Fabrice Rastello, Louis-Noël Pouchet, P. Sadayappan. 158-159 [doi]
• POSTER: NUMA-Aware Power Management for Chip MultiprocessorsChangmin Ahn, Camilo A. Celis Guzman, Bernhard Egger. 160-161 [doi]
• POSTER: BigBus: A Scalable Optical InterconnectEldhose Peter, Janibul Bashir, Smruti R. Sarangi. 162-163 [doi]
• POSTER: Elastic Reconfiguration for Heterogeneous NoCs with BiNoCHSAmirhossein Mirhosseini, Mohammad Sadrosadati, Behnaz Soltani, Hamid Sarbazi-Azad, Thomas F. Wenisch. 164-165 [doi]
• Nexus: A New Approach to Replication in Distributed Shared CachesPo-An Tsai, Nathan Beckmann, Daniel Sánchez 0003. 166-179 [doi]
• Leeway: Addressing Variability in Dead-Block Prediction for Last-Level CachesPriyank Faldu, Boris Grot. 180-193 [doi]
• Application Clustering Policies to Address System Fairness with Intel's Cache Allocation TechnologyVicent Selfa, Julio Sahuquillo, Lieven Eeckhout, Salvador Petit, Maráa Engracia Gómez. 194-205 [doi]
• Transparent Dual Memory Compression ArchitectureSeikwon Kim, Seonyoung Lee, Taehoon Kim, Jaehyuk Huh. 206-218 [doi]
• End-to-End Deep Learning of Optimization HeuristicsChris Cummins, Pavlos Petoumenos, Zheng Wang 0001, Hugh Leather. 219-232 [doi]
• Graphie: Large-Scale Asynchronous Graph Traversals on Just a GPUWei Han, Daniel Mawhirter, Bo Wu, Matthew Buland. 233-245 [doi]
• A GPU-Friendly Skiplist AlgorithmNurit Moscovici, Nachshon Cohen, Erez Petrank. 246-259 [doi]
• Sthira: A Formal Approach to Minimize Voltage Guardbands under Variation in Networks-on-Chip for Energy EfficiencyRaghavendra Pradyumna Pothukuchi, Amin Ansari, Bhargava Gopireddy, Josep Torrellas. 260-272 [doi]
• Avoiding TLB Shootdowns Through Self-Invalidating TLB EntriesAmro Awad, Arkaprava Basu, Sergey Blagodurov, Yan Solihin, Gabriel H. Loh. 273-287 [doi]
• Weak Memory Models: Balancing Definitional Simplicity and Implementation FlexibilitySizhuo Zhang, Muralidaran Vijayaraghavan, Arvind. 288-302 [doi]
• Near-Memory Address TranslationJavier Picorel, Djordje Jevdjic, Babak Falsafi. 303-317 [doi]
• Efficient Checkpointing of Loop-Based Codes for Non-volatile Main MemoryHussein Elnawawy, Mohammad Alshboul, James Tuck, Yan Solihin. 318-329 [doi]
• SuperGraph-SLP Auto-VectorizationVasileios Porpodas. 330-342 [doi]
• Exploiting Asymmetric SIMD Register Configurations in ARM-to-x86 Dynamic Binary TranslationYu-Ping Liu, Ding-Yong Hong, Jan-Jan Wu, Sheng-Yu Fu, Wei-Chung Hsu. 343-355 [doi]
• A Generalized Framework for Automatic Scripting Language ParallelizationTaewook Oh, Stephen R. Beard, Nick P. Johnson, Sergiy Popovych, David I. August. 356-369 [doi]
• Architecting a Novel Hybrid Cache with Low EnergyJiacong He, Joseph Callenes-Sloan. 370 [doi]
• Introspective ComputingKarl Taht, Rajeev Balasubramonian. 371 [doi]
• A DSL for Performance OrchestrationThiago Santos Faria Xavier Teixeira, David Padua, William Gropp. 372 [doi]
• Cache Automaton: Repurposing Caches for Automata ProcessingArun Subramaniyan 0001, Jingcheng Wang, Ezhil R. M. Balasubramanian, David Blaauw, Dennis Sylvester, Reetuparna Das. 373 [doi]
• Large Scale Data Clustering Using Memristive k-Median ComputationYomi Karthik Rupesh, Mahdi Nazm Bojnordi. 374 [doi]
• In-memory Data Flow ProcessorDaichi Fujiki, Scott A. Mahlke, Reetuparna Das. 375 [doi]
• Multilayer Compute Resource Management with Robust Control TheoryRaghavendra Pradyumna Pothukuchi, Sweta Yamini Pothukuchi, Petros G. Voulgaris, Josep Torrellas. 376 [doi]