Taras Iakymchuk, Alfredo Rosado, José V. Francés, Manuel Batallre. Fast spiking neural network architecture for low-cost FPGA devices. In Leandro Soares Indrusiak, Guy Gogniat, Nikolaos S. Voros, editors, 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), York, United Kingdom, July 9-11, 2012. pages 1-6, IEEE, 2012. [doi]
@inproceedings{IakymchukRFB12, title = {Fast spiking neural network architecture for low-cost FPGA devices}, author = {Taras Iakymchuk and Alfredo Rosado and José V. Francés and Manuel Batallre}, year = {2012}, doi = {10.1109/ReCoSoC.2012.6322906}, url = {http://dx.doi.org/10.1109/ReCoSoC.2012.6322906}, researchr = {https://researchr.org/publication/IakymchukRFB12}, cites = {0}, citedby = {0}, pages = {1-6}, booktitle = {7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), York, United Kingdom, July 9-11, 2012}, editor = {Leandro Soares Indrusiak and Guy Gogniat and Nikolaos S. Voros}, publisher = {IEEE}, isbn = {978-1-4673-2570-7}, }