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Efficient Low-Latency Multiplication Architecture for NIST Trinomials With RISC-V Integration

José Luis Imaña, Luis Piñuel, Yao-Ming Kuo, Oscar Ruano, Francisco Garcia-Herrero. Efficient Low-Latency Multiplication Architecture for NIST Trinomials With RISC-V Integration. IEEE Trans. Circuits Syst. II Express Briefs, 71(8):3915-3919, August 2024. [doi]

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