A. Neslin Ismailoglu, Murat Askar. SDIVA: Structural Delay Insensitivity Verification Analysis Method for Bit-Level Pipelined Systolic Arrays with Early Output Evaluation. In Luca Fanucci, editor, 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008. pages 566-571, IEEE, 2008. [doi]
@inproceedings{IsmailogluA08,
title = {SDIVA: Structural Delay Insensitivity Verification Analysis Method for Bit-Level Pipelined Systolic Arrays with Early Output Evaluation},
author = {A. Neslin Ismailoglu and Murat Askar},
year = {2008},
doi = {10.1109/DSD.2008.117},
url = {http://dx.doi.org/10.1109/DSD.2008.117},
tags = {analysis},
researchr = {https://researchr.org/publication/IsmailogluA08},
cites = {0},
citedby = {0},
pages = {566-571},
booktitle = {11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008},
editor = {Luca Fanucci},
publisher = {IEEE},
isbn = {978-0-7695-3277-6},
}