Megumi Ito, Moriyoshi Ohara. A power-efficient FPGA accelerator: Systolic array with cache-coherent interface for pair-HMM algorithm. In 2016 IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS XIX, Yokohama, Japan, April 20-22, 2016. pages 1-3, IEEE, 2016. [doi]
@inproceedings{ItoO16-0, title = {A power-efficient FPGA accelerator: Systolic array with cache-coherent interface for pair-HMM algorithm}, author = {Megumi Ito and Moriyoshi Ohara}, year = {2016}, doi = {10.1109/CoolChips.2016.7503681}, url = {http://dx.doi.org/10.1109/CoolChips.2016.7503681}, researchr = {https://researchr.org/publication/ItoO16-0}, cites = {0}, citedby = {0}, pages = {1-3}, booktitle = {2016 IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS XIX, Yokohama, Japan, April 20-22, 2016}, publisher = {IEEE}, isbn = {978-1-5090-1386-9}, }