A power-efficient FPGA accelerator: Systolic array with cache-coherent interface for pair-HMM algorithm - researchr publication

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Megumi Ito, Moriyoshi Ohara. A power-efficient FPGA accelerator: Systolic array with cache-coherent interface for pair-HMM algorithm. In 2016 IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS XIX, Yokohama, Japan, April 20-22, 2016. pages 1-3, IEEE, 2016. [doi]

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