Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip - researchr publication authors

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Vikram Iyengar, Krishnendu Chakrabarty. Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip. In 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA, USA. pages 368-374, IEEE Computer Society, 2001. [doi]

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