Reducing transistor count in clocked standard cells with ambipolar double-gate FETs

Kotb Jabeur, David Navarro, Ian O'Connor, Pierre-Emmanuel Gaillardon, M. Haykel Ben Jamaa, Fabien Clermidy. Reducing transistor count in clocked standard cells with ambipolar double-gate FETs. In Shamik Das, Iris Bahar, Michael T. Niemier, editors, 2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010, Anaheim, CA, USA, June 17-18, 2010. pages 47-52, IEEE Computer Society, 2010. [doi]

Authors

Kotb Jabeur

This author has not been identified. Look up 'Kotb Jabeur' in Google

David Navarro

This author has not been identified. Look up 'David Navarro' in Google

Ian O'Connor

This author has not been identified. Look up 'Ian O'Connor' in Google

Pierre-Emmanuel Gaillardon

This author has not been identified. Look up 'Pierre-Emmanuel Gaillardon' in Google

M. Haykel Ben Jamaa

This author has not been identified. Look up 'M. Haykel Ben Jamaa' in Google

Fabien Clermidy

This author has not been identified. Look up 'Fabien Clermidy' in Google