Ali Jahanian, Morteza Saheb Zamani. Improved performance and yield with chip master planning design methodology. In Fabrizio Lombardi, Sanjukta Bhanja, Yehia Massoud, R. Iris Bahar, editors, Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009. pages 185-190, ACM, 2009. [doi]
Abstract is missing.