Yogesh M. Jain, Aviraj R. Jadhav, Harish V. Dixit, Akshay S. Hindole, Jithin R. Vadakoott, Devendra Bilaye. A novel VLSI design of DCTQ processor for FPGA implementation. In 19th International Symposium on VLSI Design and Test, VDAT 2015, Ahmedabad, India, June 26-29, 2015. pages 1-5, IEEE, 2015. [doi]
@inproceedings{JainJDHVB15,
title = {A novel VLSI design of DCTQ processor for FPGA implementation},
author = {Yogesh M. Jain and Aviraj R. Jadhav and Harish V. Dixit and Akshay S. Hindole and Jithin R. Vadakoott and Devendra Bilaye},
year = {2015},
doi = {10.1109/ISVDAT.2015.7208102},
url = {http://dx.doi.org/10.1109/ISVDAT.2015.7208102},
researchr = {https://researchr.org/publication/JainJDHVB15},
cites = {0},
citedby = {0},
pages = {1-5},
booktitle = {19th International Symposium on VLSI Design and Test, VDAT 2015, Ahmedabad, India, June 26-29, 2015},
publisher = {IEEE},
isbn = {978-1-4799-1743-3},
}