Area-Efficient FPGA Implementation of Quadruple Precision Floating Point Multiplier

Manish Kumar Jaiswal, Ray C. C. Cheung. Area-Efficient FPGA Implementation of Quadruple Precision Floating Point Multiplier. In 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, IPDPS 2012, Shanghai, China, May 21-25, 2012. pages 376-382, IEEE Computer Society, 2012. [doi]

Abstract

Abstract is missing.