A new approach to minimize leakage power in nano-scale VLSI adder

P. Jamwal, M. B. Srinivas, G. V. K. Sarma, M. M. Krishna. A new approach to minimize leakage power in nano-scale VLSI adder. In B. K. Mishra, editor, Proceedings of the ICWET 10 International Conference & Workshop on Emerging Trends in Technology, Mumbai, Maharashtra, India, February 26 - 27, 2010. pages 880-886, ACM, 2010. [doi]

@inproceedings{JamwalSSK10,
  title = {A new approach to minimize leakage power in nano-scale VLSI adder},
  author = {P. Jamwal and M. B. Srinivas and G. V. K. Sarma and M. M. Krishna},
  year = {2010},
  doi = {10.1145/1741906.1742108},
  url = {http://doi.acm.org/10.1145/1741906.1742108},
  tags = {systematic-approach},
  researchr = {https://researchr.org/publication/JamwalSSK10},
  cites = {0},
  citedby = {0},
  pages = {880-886},
  booktitle = {Proceedings of the ICWET  10 International Conference & Workshop on Emerging Trends in Technology, Mumbai, Maharashtra, India, February 26 - 27, 2010},
  editor = {B. K. Mishra},
  publisher = {ACM},
  isbn = {978-1-60558-812-4},
}