FPGA Prototyping Approach for the Validation of Efficient Iterative Decoders in Digital Communication Systems - researchr publication authors

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Christophe JÃ©go. FPGA Prototyping Approach for the Validation of Efficient Iterative Decoders in Digital Communication Systems. In Toomas P. Plaks, editor, Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA 2009, July 13-16, 2009, Las Vegas Nevada, USA. pages 9-18, CSREA Press, 2009.

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