Approximate Testing of Digital VLSI Circuits using Error Significance based Fault Analysis - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Sisir Kumar Jena, Santosh Biswas, Jatindra Kumar Deka. Approximate Testing of Digital VLSI Circuits using Error Significance based Fault Analysis. In 2020 24th International Symposium on VLSI Design and Test (VDAT), Bhubaneswar, India, July 23-25, 2020. pages 1-6, IEEE, 2020. [doi]

This author has not been identified. Look up 'Sisir Kumar Jena' in GoogleThis author has not been identified. Look up 'Santosh Biswas' in GoogleThis author has not been identified. Look up 'Jatindra Kumar Deka' in Google

runs on WebDSL