Sisir Kumar Jena, Santosh Biswas, Jatindra Kumar Deka. Approximate Testing of Digital VLSI Circuits using Error Significance based Fault Analysis. In 2020 24th International Symposium on VLSI Design and Test (VDAT), Bhubaneswar, India, July 23-25, 2020. pages 1-6, IEEE, 2020. [doi]
@inproceedings{JenaBD20,
title = {Approximate Testing of Digital VLSI Circuits using Error Significance based Fault Analysis},
author = {Sisir Kumar Jena and Santosh Biswas and Jatindra Kumar Deka},
year = {2020},
doi = {10.1109/VDAT50263.2020.9190571},
url = {https://doi.org/10.1109/VDAT50263.2020.9190571},
researchr = {https://researchr.org/publication/JenaBD20},
cites = {0},
citedby = {0},
pages = {1-6},
booktitle = {2020 24th International Symposium on VLSI Design and Test (VDAT), Bhubaneswar, India, July 23-25, 2020},
publisher = {IEEE},
isbn = {978-1-7281-9369-4},
}