Hartwig Jeschke. Design Space Expoloration Chip Size Estimation for SOC Design Space Exploration. In Georgi Gaydadjiev, C. John Glossner, Jarmo Takala, Stamatis Vassiliadis, editors, Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2006), Samos, Greece, July 17-20, 2006. pages 56-62, IEEE, 2006. [doi]
Abstract is missing.