Paul G. A. Jespers. Sizing CMOS circuits by means of the gm/ID methodology and a compact model. In Marcelo Lubaszewski, Michel Renovell, Rajesh K. Gupta, editors, Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008. pages 1, ACM, 2008. [doi]
@inproceedings{Jespers08, title = {Sizing CMOS circuits by means of the gm/ID methodology and a compact model}, author = {Paul G. A. Jespers}, year = {2008}, doi = {10.1145/1404371.1404373}, url = {http://doi.acm.org/10.1145/1404371.1404373}, researchr = {https://researchr.org/publication/Jespers08}, cites = {0}, citedby = {0}, pages = {1}, booktitle = {Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008}, editor = {Marcelo Lubaszewski and Michel Renovell and Rajesh K. Gupta}, publisher = {ACM}, isbn = {978-1-60558-231-3}, }