100Gb/s ethernet chipsets in 65nm CMOS technology - researchr publication authors

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Jhih-Yu Jiang, Ping-Chuan Chiang, Hao-Wei Hung, Chen-Lun Lin, Ty Yoon, Jri Lee. 100Gb/s ethernet chipsets in 65nm CMOS technology. In 2013 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2013, San Francisco, CA, USA, February 17-21, 2013. pages 120-121, IEEE, 2013. [doi]

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